Compilers | Mahbub H. Raton

IR-Sentinel: LLVM-IR Security Analysis via MCP

Sun, 01 Feb 2026 00:00:00 +0000

Language models are good at recognizing patterns in code and bad at knowing what the compiler actually did with it. IR-Sentinel is a proof of concept that closes that gap by handing the model the compiler.

It is a Model Context Protocol (MCP) server, built on FastMCP, that exposes a local LLVM toolchain — clang and opt — as tools an AI agent can call. The agent pipeline then:

Compiles C++ source to LLVM IR,
Extracts control flow graph metrics from it,
Iteratively queries Gemini against that structured view to identify use-after-free vulnerability patterns.

The interesting part is that the model reasons over the IR and the CFG rather than over surface syntax, so it sees the program the way the optimizer does.

Built with Python, LLVM, Gemini, and FastMCP.

AEGIS: An LLVM Pass for Hardware Reliability

Fri, 01 Aug 2025 00:00:00 +0000

Transient hardware faults — a bit flipped in a cache line or a register by a stray particle or a marginal voltage — do not announce themselves. The machine keeps running and quietly produces the wrong answer. AEGIS is an LLVM pass that makes a program check its own arithmetic, so that a corrupted value is caught before it can escape.

The pass implements Error Detection by Duplicated Instructions (EDDI). It duplicates global, stack, and heap values and compares the two copies at the points where a wrong value would become observable: before a store, before a branch, and before a function call. Getting this to work on real programs meant more than duplicating instructions:

Call boundaries. Call sites are rewritten to pass shadow arguments and retrieve shadow return values, so duplication survives across function calls rather than stopping at each one.
Pointer sizes. Knowing how much memory to duplicate behind a pointer is not something the IR tells you. The pass recovers it from DWARF debug metadata, falling back to a signature table for library calls.
Extensibility. Hardening schemes are registered through a strategy registry, so adding a new one is a single self-registering file rather than an edit threaded through the pass.
Testing. A regression suite validates both that the transformation is correct and that fault-detection coverage holds across the benchmark suite.

Measured against L1 cache fault injection, AEGIS reduces silent data corruption by 1.3× to 29× across qsort, matmul, and CRC32, at a runtime cost of 1.6× to 3.0×.

Built with C++, LLVM, Clang, and CMake.

Architectural Hurdles: Exploring the Difficulties of x86-to-ARM Binary Cross-Compilation

Sun, 01 Jun 2025 00:00:00 +0000

Cross-Compiling x86 Binaries to ARM

Sat, 01 Jun 2024 00:00:00 +0000

Moving a program to a new instruction set architecture is straightforward when you have the source. When you do not, you have to reconstruct enough of the program’s meaning from the binary itself to emit correct code for a different machine.

This project extended Binrec — a dynamic binary lifting framework that recovers LLVM IR by observing concrete executions — to target AArch64 from x86 input. The work centered on two things:

Adapting the lifting pipeline. Binrec’s dynamic execution and IR recovery stages assumed an x86 target throughout; retargeting them meant separating what was genuinely architecture-neutral in the recovered IR from what had quietly encoded x86 assumptions.
A translation layer for library calls. Calls out to the C library cross the boundary where the two calling conventions disagree. An x64-to-AArch64 shim translates arguments and return values at that boundary.

The result runs two real-world SPEC CPU 2017 programs, mcf and xalancbmk, correctly on ARM, at roughly 6× slowdown relative to native.

A manuscript on the architectural mismatches this work surfaced is in preparation.

Built with LLVM, C++, S2E, and x86/ARM assembly.

WARIR: A WebAssembly Optimizing Compiler

Sat, 01 Jun 2024 00:00:00 +0000

A complete compiler pipeline from the SMPL teaching language down to WebAssembly, written for a graduate compilers course.

The back end is where most of the work went:

Graph-coloring register allocation, building the interference graph from live ranges and spilling when the graph is not colorable with the available registers.
SSA-based dataflow analysis driving common subexpression elimination and copy propagation, with the optimizations expressed as transformations on the SSA form rather than ad-hoc peephole rules.

Built with Python, Node.js, and WebAssembly.