Architecture

AEGIS: An LLVM Pass for Hardware Reliability
An LLVM transformation pass that duplicates computation and checks it before stores, branches, and calls, cutting silent data corruption by up to 29× under cache fault injection.
Architectural Fault Injection Framework
Register-file and L1 cache fault injection in gem5, plus the automation that ran a 600K-injection campaign in under 24 hours instead of 7 days.
Source
Cross-Compiling x86 Binaries to ARM
Extending the Binrec lifting framework to recompile x86 binaries for AArch64 without source, validated on two real SPEC CPU 2017 programs.
Binrec
MIPS 4 Bit Processor Design
A 4-bit MIPS processor supporting 12 instructions, designed and validated in the Logisim simulator.
Code
MIPS 4 Bit Processor Design